FIG. 1a illustrates a circuit 10 illustrating a conventional approach to implementing a multiplexer. The circuit 10 comprises a multiplexer 11 and a decoder 12. The multiplexer 11 presents a first signal (i.e., a) or a second signal (i.e., b) in response to a control signal generated by the decoder 12. The decoder 12 may generate the control signal in response to the select signal (i.e., SELO). FIG. 1b shows a more detailed diagram of the multiplexer 11. The multiplexer 11 comprises a number of stages 13a-13n. The stage 13a comprises a number of transistor pairs 14a-14b and the stage 13n comprises a number of transistor pairs 16a-16b. Each of the transistor pairs receives a differential input signal (e.g., A and An or B and Bn, respectively). A number of select transistors 18a-18n respond to a number of control signals (i.e., SEL_A and SEL_B) generated by the decoder 12. An example of the circuit 10 may be found in copending application, U.S. Ser. No. 09/182,556, filed on Oct. 19, 1998, entitled HIGH-SPEED, MULTIPLE-INPUT MULTIPLEXER SCHEME, which is hereby incorporated by reference in its entirety. The circuit 10 comprises N single ended select lines that are used for an N-input multiplexer. Only one select line is selected at a given time. This activates the selected stage 13a-13n while the non-selected stages are de-activated.
The circuit 10 is particularly useful for applications that have CML-type inputs and CML-type outputs. However, the circuit 10 may not be as useful where large output swings are required. For example, where the output swings higher than standard CML levels (e.g., 400 mV), the base collector may start leaking, and, in the extreme case, even forward bias. An additional limitation occurs when the input to the multiplexer 11 runs across two different power supplies. This means that potentially Vcb=Vswing+power supply drop (e.g., 0.4 v+0.2 v=0.6 v). Again, the base to collector junction could be forward biased.
Some of the disadvantages of the circuit 10 can be solved by adding an emitter follower on the input. However, such an approach generally requires three-level gating, which may not be practical for 3.3V supplies.
Referring to FIG. 2a, a circuit 50 is shown that can be used for instances where large output swings are required or an interface between two power supply zones is required. The circuit 50 generally comprises a multiplexer 52, a decoder 54 and a boost circuit 56. The multiplexer 52 is similar to the circuit 10. The boost circuit 56 may comprise a transistor 58, a transistor 60, a transistor 62, a transistor 64 and a number of current sources 66a-66n. A CML multiplexer can be used to do the functional selects followed by a swing boost circuit which contains an emitter follower (level shift) to keep the Vbc on the differential pair from forward biasing.
The circuit 50 has limitations associated with current, layout, stage distortion, noise induced distortion, matching, delay, and output swing variability. The additional circuitry generally increases the overall current use. The additional circuitry also generally increases the layout of the circuit 50 and increases distortion. Noise induced distortion can be caused if an additional buffer is far enough from the multiplexer 52. Power supply noise could be an issue it both buffers do not experience identical noise environment. This could result in noise induced distortion when matching two data paths (such as in an output buffer application where a pump up signal is matched to a pump down signal) . The circuit 50 requires matching two buffers to two other buffers. The two stages will have a larger delay than desired. Output swing variability is difficult to achieve in the output level swing of the circuit 50 (or the circuit 10).